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r01ds0010ej0200 rev.2.00 page 1 of 45 may 31, 2012 r8c/m11a group, r8c/m12a group renesas mcu datasheet 1. overview 1.1 features the r8c/m11a group and r8c/m12a group of single-chip microcontrollers (mcus) incorporate the r8c cpu core, which provides sophisticated instructions for a high level of efficiency. with 1 mbyte of address space, the cpu core is capable of executi ng instructions at high speed. in addition , it features a mult iplier for high-speed arithmetic processing. power consumption is low, and the supported operating modes allow additional power control. these mcus are designed to maximize emi/ems performance. integration of many peripheral functions on the same ch ip, including multifunction timer and serial interface, reduces the number of system components. the r8c/m11a group and r8c/m12a group include data flash (1 kb 2 blocks). 1.1.1 applications home appliances, office equipment, audio equipment, consumer products, etc. r01ds0010ej0200 rev.2.00 may 31, 2012
r8c/m11a group, r8c/m12a group 1. overview r01ds0010ej0200 rev.2.00 page 2 of 45 may 31, 2012 1.1.2 differences between groups table 1.1 lists the specification comparison between r8c/m11a group and r8c/m12a group. the explanations in 1.1.3 and subsequent sections apply to the r8c/m12a group specifications only, unless otherwise specified. table 1.1 specification comparison between r8c/m11a group and r8c/m12a group item function r8c/m11a group r8c/m12a group interrupts external interrupt inputs 6 (int 3, key input 3) 8 (int 4, key input 4) i/o ports number of pins 14 non-provided pins: p1_0/an0/trciod/ki0 p3_3/ivcmp3/trcclk/int3 p3_4/ivref3/trcioc/int2 p3_5/trciod/ki2 /vcout3 p4_2/trbo/txd0/ki3 p4_5/int0 /adtrg 20 number of cmos i/o ports 11 non-provided ports: p1_0, p3_3, p3_4, p3_5, p4_2, p4_5 17 number of high-current drive ports 5 non-provided ports: p3_3, p3_4, p3_5 8 a/d converter number of a/d channels 5 channels non-provided port: an0 6 channels comparator b number of channels comparator b1 comparator b1, comparator b3
r8c/m11a group, r8c/m12a group 1. overview r01ds0010ej0200 rev.2.00 page 3 of 45 may 31, 2012 table 1.2 lists the r8c/m11a group register setti ngs. these settings correspond to the specification differences between the r8c/m11a group and r8c/m12a group. table 1.2 r8c/m11a group register settings related function register name address bit setting method for access int3 inten 00038h int3en reserved bit. set to 0. intf0 0003ah int3f0, int3f1 reserved bits. set to 0. iscr0 0003ch int3sa, int3sb reserved bits. set to 0. ilvld 0004dh ilvld0, ilvld1 reserved bits. set to 0. irr3 00053h iri3 reserved bit. set to 0. ki0 kien 0003eh ki0en, ki0pl reserved bits. set to 0. comparator b3 interrupt ilvl2 00042h ilvl24, ilvl25 reserved bits. set to 0. irr2 00052h ircmp3 reserved bit. set to 0. p1_0 pd1 000a9h pd1_0 reserved bit. set to 0. p1 000afh p1_0 reserved bit. set to 0. pur1 000b5h pu1_0 reserved bit. set to 0. pod1 000c1h pod1_0 reserved bit. set to 0. pml1 000c8h p10sel0, p10sel1 reserved bits. set to 0. p3_3, p3_4, p3_5 pd3 000abh pd3_3, pd3_4, pd3_5 reserved bits. set to 0. p3 000b1h p3_3, p3_4, p3_5 reserved bits. set to 0. pur3 000b7h pu3_3, pu3_4, pu3_5 reserved bits. set to 0. drr3 000bdh drr3_3, drr3_4, drr3_5 reserved bits. set to 0. pod3 000c3h pod3_3, pod3_4, pod3_5 reserved bits. set to 0. pml3 000cch p33sel0, p33sel1 reserved bits. set to 0. pmh3 000cdh p34sel0, p34sel1, p35sel0, p35sel1 reserved bits. set to 0. p4_2, p4_5 pd4 000ach pd4_2, pd4_5 reserved bits. set to 0. p4 000b2h p4_2, p4_5 reserved bits. set to 0. pur4 000b8h pu4_2, pu4_5 reserved bits. set to 0. pod4 000c4h pod4_2, pod4_5 reserved bits. set to 0. pml4 000ceh p42sel0, p42sel1 reserved bits. set to 0. pmh4 000cfh p45sel0, p45sel1 reserved bits. set to 0. an0 adinsel 0009dh ch0, adgsel0, adgsel1 do not set to 000. comparator b3 wcmpr 00180h wcb3m0, wcb3out reserved bits. set to 0. wcb3intr 00182h all bits reserved register. no access is allowed.
r8c/m11a group, r8c/m12a group 1. overview r01ds0010ej0200 rev.2.00 page 4 of 45 may 31, 2012 1.1.3 specifications tables 1.3 and 1.4 outline the specifications. table 1.3 specifications (1) item function description cpu central processing unit r8c cpu core ? number of fundamental instructions: 89 ? minimum instruction execution time: 50 ns (f(xin) = 20 mhz, vcc = 2.7 v to 5.5 v) 200 ns (f(xin) = 5 mhz, vcc = 1.8 v to 5.5 v) ? multiplier: 16 bits 16 bits 32 bits ? multiply-accumulate instruction: 16 bits 16 bits + 32 bits 32 bits ? operating mode: single-chip mode (address space: 1 mbyte) memory rom, ram, data flash see table 1.5 product list . reset sources ? hardware reset by reset ? power-on reset ? watchdog timer reset ? software reset ? reset by voltage detection 0 voltage detection voltage detection circuit voltage detection with two check points: voltage detection 0, voltage detect ion 1 (detection levels selectable) watchdog timer ? 14 bits 1 (with prescaler) ? reset start function selectable ? count source protection function selectable ? periodic timer function selectable clock clock generation circuits ? 3 circuits: xin clock oscillation circuit, high-speed on-chip oscillator (wit h frequency adjustment function), low-speed on-chip oscillator ? oscillation stop detection: xin cl ock oscillation stop detection function ? clock frequency divider circuit integrated power control ? standard operating mode ? wait mode (cpu stopped, peripheral functions in operation) ? stop mode (cpu and peripheral functions stopped) interrupts ? number of interrupt vectors: 69 ? external interrupt inputs: 8 (int 4, key input 4) ? priority levels: 2 i/o ports programmable i/o ports ? cmos i/o: 17 (pull-up resistor selectable) ? high-current drive ports: 8 timer timer rj2 16 bits 1 timer mode, pulse output mode (out put level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode timer rb2 8 bits 1 (with 8-bit prescaler) or 16 bits 1 (selectable) timer mode, programmab le waveform generation mode (pwm output), programmable one-shot generation mode, programmable wait one-shot generation mode timer rc 16 bits 1 (with 4 capture/compare registers) timer mode (output compare func tion, input capt ure function), pwm mode (3 outputs), pwm2 mode (1 pwm output) serial interface uart0 clock synchronous serial i/o. also used for asynchronous serial i/o. a/d converter ? resolution: 10 bits 6 channels ? sample and hold function, sweep mode comparator b 2 circuits
r8c/m11a group, r8c/m12a group 1. overview r01ds0010ej0200 rev.2.00 page 5 of 45 may 31, 2012 note: 1. specify the d version if it is to be used. table 1.4 specifications (2) item function description flash memory ? program/erase voltage fo r program rom: vcc = 1.8 v to 5.5 v ? program/erase voltage for data flash: vcc = 1.8 v to 5.5 v ? program/erase endurance:10,000 times (data flash) 10,000 times (program rom) ? program security: id code check, protection enabled by lock bit ? debug functions: on-chip debug, on-board flash rewrite function operating frequency/ power supply voltage f(xin) = 20 mhz (vcc = 2.7 v to 5.5 v) f(xin) = 5 mhz (vcc = 1.8 v to 5.5 v) temperature range -20 c to 85 c (n version) -40 c to 85 c (d version) (1) package 14-pin tssop: [package code] ptsp0014ja-b 14-pin dip: [package code] prdp0014ac-a 20-pin lssop: [package code] plsp0020jb-a 20-pin dip: [package code] prdp0020ad-a
r8c/m11a group, r8c/m12a group 1. overview r01ds0010ej0200 rev.2.00 page 6 of 45 may 31, 2012 1.2 product list table 1.5 lists the product list. figure 1.1 shows the product part number structure. figure 1.1 product part number structure table 1.5 product list group name part no. internal rom capacity internal ram capacity package type remarks program rom data flash r8c/m11a group r5f2m110ansp 2 kbytes 1 kbyte 2 256 bytes ptsp0014ja-b n version r5f2m111ansp 4 kbytes 1 kbyte 2 384 bytes r5f2m112ansp 8 kbytes 1 kbyte 2 512 bytes r5f2m110andd 2 kbytes 1 kbyte 2 256 bytes prdp0014ac-a r5f2m111andd 4 kbytes 1 kbyte 2 384 bytes r5f2m112andd 8 kbytes 1 kbyte 2 512 bytes r5f2m110adsp 2 kbytes 1 kbyte 2 256 bytes ptsp0014ja-b d version r5f2m111adsp 4 kbytes 1 kbyte 2 384 bytes r5f2m112adsp 8 kbytes 1 kbyte 2 512 bytes r8c/m12a group r5f2m120ansp 2 kbytes 1 kbyte 2 256 bytes plsp0020jb-a n version r5f2m121ansp 4 kbytes 1 kbyte 2 384 bytes r5f2m122ansp 8 kbytes 1 kbyte 2 512 bytes r5f2m120andd 2 kbytes 1 kbyte 2 256 bytes prdp0020ad-a r5f2m121andd 4 kbytes 1 kbyte 2 384 bytes r5f2m122andd 8 kbytes 1 kbyte 2 512 bytes r5f2m120adsp 2 kbytes 1 kbyte 2 256 bytes plsp0020jb-a d version r5f2m121adsp 4 kbytes 1 kbyte 2 384 bytes r5f2m122adsp 8 kbytes 1 kbyte 2 512 bytes current of may 2012 part no. r 5 f 2mx x x a n sp package type: sp: ptsp0014ja-b, plsp0020jb-a dd: prdp0014ac-a, prdp0020ad-a classification n: operating ambient temperature -20 c to 85 c d: operating ambient temperature -40 c to 85 c rom capacity 0: 2 kb 1: 4 kb 2: 8 kb number of pins 1: 14 pins 2: 20 pins r8c/mxxa group r8c/mx series memory type f: flash memory renesas mcu renesas semiconductor
r8c/m11a group, r8c/m12a group 1. overview r01ds0010ej0200 rev.2.00 page 7 of 45 may 31, 2012 1.3 block diagram figure 1.2 shows the block diagram. figure 1.2 block diagram i/o ports watchdog timer (14 bits) system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator timers timer rj2 (16 bits 1) timer rb2 (8 bits 1 or 16 bits 1) timer rc (16 bits 1) a/d converter (10 bits 6 channels) uart clock synchronous serial i/o clock asynchronous serial i/o peripheral functions voltage detection circuit ram (2) multiplier sb usp intb isp flg pc r8c cpu core memory rom (1) r0h r1h r2 r3 r0l r1l a0 fb a1 notes: 1. rom size varies with the product. 2. ram size varies with the product. port p1 8 port p3 4 port p4 4 comparator b port pa 1
r8c/m11a group, r8c/m12a group 1. overview r01ds0010ej0200 rev.2.00 page 8 of 45 may 31, 2012 1.4 pin assignment figures 1.3 and 1.4 show pin assignment (top view). table 1.6 lists the pin name information by pin number. figure 1.3 r8c/m11a group pin assignment (top view) figure 1.4 r8c/m12a group pin assignment (top view) 3 4 6 7 p3_7/adtrg/trjo/trciod reset/pa_0 p4_7/xout/int2 vss/avss p4_6/xin/rxd0/txd0/int1/ vcout1/trjio vcc/avcc mode 14 13 12 11 10 9 8 p1_1/an1/trcioa/trctrg/ki1 p1_2/an2/trciob/ki2 p1_3/an3/trcioc/ki3/trbo p1_4/an4/txd0/rxd0/int0/trciob p1_5/rxd0/trjio/int1/vcout1 p1_6/ivref1/clk0/trjo/trciob p1_7/an7/ivcmp1/int1/trjio/trcclk r8c/m11a group ptsp0014ja-b prdp0014ac-a (top view) 1 2 5 note: 1. confirm the pin 1 position on the package by referring to package dimensions . 6 p4_2/trbo/txd0/ki3 p3_7/adtrg/trjo/trciod reset/pa_0 p4_7/xout/int2 vss/avss p4_6/xin/rxd0/txd0/int1/ vcout1/trjio vcc/avcc mode p3_5/trciod/ki2/vcout3 p3_4/ivref3/trcioc/int2 20 19 18 17 16 15 14 13 12 11 p1_0/an0/trciod/ki0 p1_1/an1/trcioa/trctrg/ki1 p1_2/an2/trciob/ki2 p1_3/an3/trcioc/ki3/trbo p1_4/an4/txd0/rxd0/int0/trciob p1_5/rxd0/trjio/int1/vcout1 p1_6/ivref1/clk0/trjo/trciob p1_7/an7/ivcmp1/int1/trjio/trcclk p4_5/int0/adtrg p3_3/ivcmp3/trcclk/int3 1 2 3 4 5 7 8 9 10 r8c/m12a group plsp0020jb-a prdp0020ad-a (top view) note: 1. confirm the pin 1 position on the package by referring to package dimensions .
r8c/m11a group, r8c/m12a group 1. overview r01ds0010ej0200 rev.2.00 page 9 of 45 may 31, 2012 table 1.6 pin name information by pin number pin number control pin port i/o pins for peripheral functions r8c/m11a group r8c/m12a group interrupt timer serial interface a/d converter, comparator b 1p4_2 ki3 trbo txd0 1 2 p3_7 trjo/trciod adtrg 23 reset pa_0 3 4 xout p4_7 int2 4 5 vss/avss 56xinp4_6 int1 trjio rxd0/txd0 vcout1 67vcc/avcc 78mode 9p3_5 ki2 trciod vcout3 10 p3_4 int2 trcioc ivref3 11 p3_3 int3 trcclk ivcmp3 12 p4_5 int0 adtrg 813 p1_7 int1 trjio/trcclk an7/ivcmp1 9 14 p1_6 trjo/trciob clk0 ivref1 10 15 p1_5 int1 trjio rxd0 vcout1 11 16 p1_4 int0 trciob rxd0/txd0 an4 12 17 p1_3 ki3 trbo/trcioc an3 13 18 p1_2 ki2 trciob an2 14 19 p1_1 ki1 trcioa/trctrg an1 20 p1_0 ki0 trciod an0
r8c/m11a group, r8c/m12a group 1. overview r01ds0010ej0200 rev.2.00 page 10 of 45 may 31, 2012 1.5 pin functions table 1.7 lists the pin functions. note: 1. contact the oscillator manufacture r for oscillation characteristics. table 1.7 pin functions item pin name i/o description power supply input vcc, vss ? apply 1.8 v through 5.5 v to the vcc pin. apply 0 v to the vss pin. analog power supply input avcc, avss ? power supply input for the a/d converter. connect a capacitor between pins avcc and avss. reset input reset i applying a low level to this pin resets the mcu. mode mode i connect this pin to the vcc pin via a resistor. xin clock input xin i i/o for the xin clock generation circuit. connect a ceramic resonator or a crystal oscillator between pins xin and xout. (1) to use an external clock, input it to the xin pin. p4_7 can be used as an i/o port at this time. xin clock output xout o int interrupt input int0 to int3 i int interrupt input. key input interrupt ki0 to ki3 i key input interrupt input. i/o ports p1_0 to p1_7, p3_0 to p3_5, p3_7, p4_2, p4_5 to p4_7, pa_0 i/o cmos i/o ports. each port has an i/o select direction register, enabling switching input and output for each port. for input ports other than pa_0, the presence or absence of a pull-up resistor can be selected by a program. p1_2 to p1_5, p3_3 to p3_5, and p3_7 can be used as led drive ports. timer rj2 trjio i/o timer rj2 i/o. trjo o timer rj2 output. timer rb2 trbo o timer rb2 output. timer rc trcclk i external clock input. trctrg i external trigger input. trcioa, trciob, trcioc, trciod i/o timer rc i/o. serial interface clk0 i/o transfer clock i/o. rxd0 i serial data input. txd0 o serial data output. a/d converter an0 to an4, an7 i analog input for the a/d converter. adtrg i external trigger input for the a/d converter. comparator b ivcmp1, ivcmp3 i analog voltage input for comparator b. ivref1, ivref3 i reference voltage input for comparator b. vcout1, vcout3 o comparison result output for comparator b.
r8c/m11a group, r8c/m12a group 2 . central processing unit (cpu) r01ds0010ej0200 rev.2.00 page 11 of 45 may 31, 2012 2. central processi ng unit (cpu) figure 2.1 shows the 13 cpu registers. the registers, r0, r1, r2, r3, a0, a1, and fb form a single register bank. the cpu has two register banks. figure 2.1 cpu registers the higher 4 bits of intb are intbh and the lower 16 bits of intb are intbl. interrupt table register data registers (1) address registers (1) frame base register (1) user stack pointer interrupt stack pointer static base register program counter carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved bits processor interrupt priority level reserved bit note: 1. these registers form a single register bank. the cpu has two register banks. flag register r3 r2 b31 b0 b15 fb r2 r3 a0 a1 r0h (r0 high-order byte) r1h (r1 high-order byte) r0l (r0 low-order byte) r1l (r1 low-order byte) intbh b19 b0 intbl b15 pc b19 b0 b15 b0 usp isp sb b15 b0 flg b15 b0 b8 b7 c d z s b o i u ipl b8 b7
r8c/m11a group, r8c/m12a group 2 . central processing unit (cpu) r01ds0010ej0200 rev.2.00 page 12 of 45 may 31, 2012 2.1 data registers (r 0, r1, r2, and r3) r0 is a 16-bit register for transfer, arithmetic, and logic operations. the same applies to r1 through r3. r0 can be split into high-order (r0h) and low-order (r0l) re gisters to be used separate ly as 8-bit data registers. the same applies to r1h and r1l. r2 can be combined with r0 and used as a 32-bit data register (r2r0). in the same way as with r0 and r2, r3 and r1 can be used as a 32-bit data register (r3r1). 2.2 address registers (a0 and a1) a0 is a 16-bit register for address register indirect addr essing and address register relative addressing. it is also used for transfer, arithmetic, and logic operations. a1 f unctions in the same manner as a0. a1 can be combined with a0 and used as a 32-bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register used for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register that indicates the start address of a re locatable interrupt vector table. 2.5 program counter (pc) pc is a 20-bit register that indicates the address of the next instruction to be executed. 2.6 user stack pointer (usp) a nd interrupt stack pointer (isp) the stack pointers (sp), usp and isp, are each 16 bits wi de. the u flag of the flg register is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register used for sb relative addressing. 2.8 flag register (flg) flg is an 11-bit register th at indicates the cpu state. 2.8.1 carry flag (c) the c flag retains carry, borrow, or shift-out bits that have been generated in th e arithmetic and logic unit. 2.8.2 debug flag (d) the d flag is for debugging only. it must only be set to 0. 2.8.3 zero flag (z) the z flag is set to 1 when an arithmetic operation results in 0. otherwise it is set to 0. 2.8.4 sign flag (s) the s flag is set to 1 when an arithmetic operation results in a negative value. otherwise it is set to 0. 2.8.5 register bank select flag (b) register bank 0 is selected when the b flag is 0. register bank 1 is selected when this flag is 1. 2.8.6 overflow flag (o) the o flag is set to 1 when an operation resu lts in an overflow. otherwise it is set to 0.
r8c/m11a group, r8c/m12a group 2 . central processing unit (cpu) r01ds0010ej0200 rev.2.00 page 13 of 45 may 31, 2012 2.8.7 interrupt enable flag (i) the i flag enables maskable interrupts. interrupts are disabled when the i fl ag is 0, and are enabled when the i flag is 1. the i flag is set to 0 when an interrupt request is acknowledged. 2.8.8 stack pointer select flag (u) isp is selected when the u flag is 0. usp is selected when the u flag is 1. the u flag is set to 0 when a hardware interrupt request is acknowledged or the int instruc tion for a software interrupt numbered from 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns eight processor interrupt priority levels from 0 to 7. if a requested interrupt has higher priority than ipl, the interrupt is enabled. if ipl is set to levels from 2 to 7, all maskable interrupt requests are disabled. 2.8.10 reserved bit the write value must be 0. the read value is undefined.
r8c/m11a group, r8c/m12a group 3. address space r01ds0010ej0200 rev.2.00 page 14 of 45 may 31, 2012 3. address space 3.1 memory map figure 3.1 shows the memory map. the r8c/m11a group and r8c/m12a group have a 1-mbyte address space from addresses 00000h to fffffh. the internal rom (program rom) is allocated at lower addre sses, beginning with address 0ffffh. for example, an 8-kbyte internal rom ar ea is allocated at addr esses 0e000h to 0ffffh. the fixed interrupt vector ta ble is allocated at addresse s 0ffdch to 0ffffh. the star t address of each interrupt routine is stored here. the internal rom (data flash) is allocated at addresses 03000h to 037ffh. the internal ram is allocated at higher addresses, beginning with address 00400h. for example, a 512-byte internal ram area is allocated at addresses 00400h to 005ffh. the internal ram is used not only for data storage but also as a stack area when a subroutine is calle d or when an interrupt request is acknowledged. special function registers (sfrs) are allocated at addresse s 00000h to 002ffh. peripheral function control registers are allocated here. all un allocated spaces within the sfrs are re served and cannot be accessed by users. figure 3.1 memory map notes: 1. data flash indicates block a (1 kbyte) and block b (1 kbyte). 2. the blank areas are reserved. no access is allowed. 0xxxxh 00000h internal rom (program rom) internal ram sfr (see 3.2 special function registers (sfrs) ) internal rom (data flash) (1) expanded area 002ffh 03000h 037ffh 0yyyyh 0ffffh fffffh 00400h 0ffffh 0ffdch 0ffd8h watchdog timer, oscillation stop detection, voltage monitor 1 undefined instruction overflow brk instruction address match single-step (reserved) (reserved) reset reserved area part number r5f2m110ansp, r5f2m110andd, r5f2m110adsp, r5f2m120ansp, r5f2m120andd, r5f2m120adsp r5f2m111ansp, r5f2m111andd, r5f2m111adsp, r5f2m121ansp, r5f2m121andd, r5f2m121adsp r5f2m112ansp, r5f2m112andd, r5f2m112adsp, r5f2m122ansp, r5f2m122andd, r5f2m122adsp capacity address 0yyyyh 2 kbytes 4 kbytes 8 kbytes 0f800h 0f000h 0e000h internal rom address 0xxxxh capacity 256 bytes 384 bytes 512 bytes 004ffh 0057fh 005ffh internal ram
r8c/m11a group, r8c/m12a group 3. address space r01ds0010ej0200 rev.2.00 page 15 of 45 may 31, 2012 3.2 special function registers (sfrs) an sfr (special function register) is a control register for a peripheral function. tables 3.1 to 3.8 list the sfr information. table 3.9 lists the id code area and option function select area. notes: 1. the blank areas are reserved. no access is allowed. 2. the mstini bit in the ofs2 register is 0. 3. the mstini bit in the ofs2 register is 1. 4. the csproini bit in the ofs register is 0. 5. the csproini bit in the ofs register is 1. table 3.1 sfr information (1) (1) address register name symbol after reset 00000h 00001h 00002h 00003h 00004h 00005h 00006h 00007h 00008h 00009h 0000ah 0000bh 0000ch 0000dh 0000eh 0000fh 00010h processor mode register 0 pm0 00h 00011h 00012h module standby control register mstcr 00h (2) 01110111b (3) 00013h protect register prcr 00h 00014h 00015h 00016h hardware reset protect register hrpr 00h 00017h 00018h 00019h 0001ah 0001bh 0001ch 0001dh 0001eh 0001fh 00020h external clock control register exckcr 00h 00021h high-speed/low-speed on-chip oscillator control register ococr 00h 00022h system clock f control register sckcr 00h 00023h system clock f select register phisel 00h 00024h clock stop control register ckstpr 00h 00025h clock control register when returning from modes ckrscr 00h 00026h oscillation stop detection register bakcr 00h 00027h 00028h 00029h 0002ah 0002bh 0002ch 0002dh 0002eh 0002fh 00030h watchdog timer function register risr 10000000b (4) 00h (5) 00031h watchdog timer reset register wdtr xxh 00032h watchdog timer start register wdts xxh 00033h watchdog timer control register wdtc 01xxxxxxb 00034h count source protection mode register cspr 10000000b (4) 00h (5) 00035h periodic timer interrupt control register wdtir 00h 00036h 00037h 00038h external input enable register inten 00h 00039h
r8c/m11a group, r8c/m12a group 3. address space r01ds0010ej0200 rev.2.00 page 16 of 45 may 31, 2012 x: undefined notes: 1. the blank areas are reserved. no access is allowed. 2. the lvdas bit in the ofs register is 0. 3. the lvdas bit in the ofs register is 1. 4. the value after a reset differs depending on the reset source. table 3.2 sfr information (2) (1) address register name symbol after reset 0003ah int input filter select register 0 intf0 00h 0003bh 0003ch int input edge select register 0 iscr0 00h 0003dh 0003eh key input enable register kien 00h 0003fh 00040h interrupt priority level register 0 ilvl0 00h 00041h 00042h interrupt priority level register 2 ilvl2 00h 00043h interrupt priority level register 3 ilvl3 00h 00044h interrupt priority level register 4 ilvl4 00h 00045h interrupt priority level register 5 ilvl5 00h 00046h interrupt priority level register 6 ilvl6 00h 00047h interrupt priority level register 7 ilvl7 00h 00048h interrupt priority level register 8 ilvl8 00h 00049h interrupt priority level register 9 ilvl9 00h 0004ah interrupt priority level register a ilvla 00h 0004bh interrupt priority level register b ilvlb 00h 0004ch interrupt priority level register c ilvlc 00h 0004dh interrupt priority level register d ilvld 00h 0004eh interrupt priority level register e ilvle 00h 0004fh 00050h interrupt monitor flag register 0 irr0 00h 00051h interrupt monitor flag register 1 irr1 00h 00052h interrupt monitor flag register 2 irr2 00h 00053h external interrupt flag register irr3 00h 00054h 00055h 00056h 00057h 00058h voltage monitor circuit edge select register vcac 00h 00059h 0005ah voltage detect register 2 vca2 00100100b (2) 00000100b (3) 0005bh voltage detection 1 level select register vd1ls 00000111b 0005ch voltage monitor 0 circuit control register vw0c 1100x011b (2) 1100x010b (3) 0005dh voltage monitor 1 circuit control register vw1c 10001010b 0005eh 0005fh reset source determination register rstfr 0000xxxxb (4) 00060h 00061h 00062h 00063h 00064h high-speed on-chip oscillator 18.432 mhz control register 0 fr18s0 value when shipped 00065h high-speed on-chip oscillator 18.432 mhz control register 1 fr18s1 value when shipped 00066h 00067h high-speed on-chip oscillator control register 1 frv1 value when shipped 00068h high-speed on-chip oscillator control register 2 frv2 value when shipped 00069h 0006ah 0006bh 0006ch 0006dh 0006eh 0006fh 00070h 00071h 00072h 00073h 00074h 00075h 00076h 00077h 00078h 00079h
r8c/m11a group, r8c/m12a group 3. address space r01ds0010ej0200 rev.2.00 page 17 of 45 may 31, 2012 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.3 sfr information (3) (1) address register name symbol after reset 0007ah 0007bh 0007ch 0007dh 0007eh 0007fh 00080h uart0 transmit/receive mode register u0mr 00h 00081h uart0 bit rate register u0brg xxh 00082h uart0 transmit buffer register u0tbl xxh 00083h u0tbh xxh 00084h uart0 transmit/receive control register 0 u0c0 00001000b 00085h uart0 transmit/receive control register 1 u0c1 00000010b 00086h uart0 receive buffer register u0rbl xxh 00087h u0rbh xxh 00088h uart0 interrupt flag and enable register u0ir 00h 00089h 0008ah 0008bh 0008ch 0008dh 0008eh 0008fh 00090h 00091h 00092h 00093h 00094h 00095h 00096h 00097h 00098h a/d register 0 ad0l xxh 00099h ad0h 000000xxb 0009ah a/d register 1 ad1l xxh 0009bh ad1h 000000xxb 0009ch a/d mode register admod 00h 0009dh a/d input select register adinsel 00h 0009eh a/d control register 0 adcon0 00h 0009fh a/d interrupt control status register adicsr 00h 000a0h 000a1h 000a2h 000a3h 000a4h 000a5h 000a6h 000a7h 000a8h 000a9h port p1 direction register pd1 00h 000aah 000abh port p3 direction register pd3 00h 000ach port p4 direction register pd4 00h 000adh port pa direction register pda 00h 000aeh 000afh port p1 register p1 00h 000b0h 000b1h port p3 register p3 00h 000b2h port p4 register p4 00h 000b3h port pa register pa 00h 000b4h 000b5h pull-up control register 1 pur1 00h 000b6h 000b7h pull-up control register 3 pur3 00h 000b8h pull-up control register 4 pur4 00h 000b9h port i/o function control register pinsr 00h 000bah 000bbh drive capacity control register 1 drr1 00h 000bch 000bdh drive capacity control register 3 drr3 00h 000beh 000bfh
r8c/m11a group, r8c/m12a group 3. address space r01ds0010ej0200 rev.2.00 page 18 of 45 may 31, 2012 notes: 1. the blank areas are reserved. no access is allowed. 2. the tcnt16 bit in the trbmr register is 0. 3. the tcnt16 bit in the trbmr register is 1. table 3.4 sfr information (4) (1) address register name symbol after reset 000c0h 000c1h open-drain control register 1 pod1 00h 000c2h 000c3h open-drain control register 3 pod3 00h 000c4h open-drain control register 4 pod4 00h 000c5h port pa mode control register pamcr 00010001b 000c6h 000c7h 000c8h port 1 function mapping register 0 pml1 00h 000c9h port 1 function mapping register 1 pmh1 00h 000cah 000cbh 000cch port 3 function mapping register 0 pml3 00h 000cdh port 3 function mapping register 1 pmh3 00h 000ceh port 4 function mapping register 0 pml4 00h 000cfh port 4 function mapping register 1 pmh4 00h 000d0h 000d1h port 1 function mapping expansion register pmh1e 00h 000d2h 000d3h 000d4h 000d5h port 4 function mapping expansion register pmh4e 00h 000d6h 000d7h 000d8h timer rj counter register trj ffh 000d9h ffh 000dah timer rj control register trjcr 00h 000dbh timer rj i/o control register trjioc 00h 000dch timer rj mode register trjmr 00h 000ddh timer rj event select register trjisr 00h 000deh timer rj interrupt control register trjir 00h 000dfh 000e0h timer rb control register trbcr 00h 000e1h timer rb one-shot control register trbocr 00h 000e2h timer rb i/o control register trbioc 00h 000e3h timer rb mode register trbmr 00h 000e4h timer rb prescaler register (2) timer rb primary/secondary register (lower 8 bits) (3) trbpre ffh 000e5h timer rb primary register (2) timer rb primary register (higher 8 bits) (3) trbpr ffh 000e6h timer rb secondary register (2) timer rb secondary register (higher 8 bits) (3) trbsc ffh 000e7h timer rb interrupt control register trbir 00h 000e8h timer rc counter trccnt 00h 000e9h 00h 000eah timer rc general register a trcgra ffh 000ebh ffh 000ech timer rc general register b trcgrb ffh 000edh ffh 000eeh timer rc general register c trcgrc ffh 000efh ffh 000f0h timer rc general register d trcgrd ffh 000f1h ffh 000f2h timer rc mode register trcmr 01001000b 000f3h timer rc control register 1 trccr1 00h 000f4h timer rc interrupt enable register trcier 01110000b 000f5h timer rc status register trcsr 01110000b 000f6h timer rc i/o control register 0 trcior0 10001000b 000f7h timer rc i/o control register 1 trcior1 10001000b 000f8h timer rc control register 2 trccr2 00011000b 000f9h timer rc digital filter function select register trcdf 00h 000fah timer rc output enable register trcoer 01111111b 000fbh timer rc a/d conversion trigger control register trcadcr 11110000b 000fch timer rc waveform output manipulation register trcopr 00h 000fdh 000feh 000ffh
r8c/m11a group, r8c/m12a group 3. address space r01ds0010ej0200 rev.2.00 page 19 of 45 may 31, 2012 note: 1. the blank areas are reserved. no access is allowed. table 3.5 sfr information (5) (1) address register name symbol after reset 00100h 00101h 00102h 00103h 00104h 00105h 00106h 00107h 00108h 00109h 0010ah 0010bh 0010ch 0010dh 0010eh 0010fh 00110h 00111h 00112h 00113h 00114h 00115h 00116h 00117h 00118h 00119h 0011ah 0011bh 0011ch 0011dh 0011eh 0011fh 00120h 00121h 00122h 00123h 00124h 00125h 00126h 00127h 00128h 00129h 0012ah 0012bh 0012ch 0012dh 0012eh 0012fh 00130h 00131h 00132h 00133h 00134h 00135h 00136h 00137h 00138h 00139h 0013ah 0013bh 0013ch 0013dh 0013eh 0013fh
r8c/m11a group, r8c/m12a group 3. address space r01ds0010ej0200 rev.2.00 page 20 of 45 may 31, 2012 note: 1. the blank areas are reserved. no access is allowed. table 3.6 sfr information (6) (1) address register name symbol after reset 00140h 00141h 00142h 00143h 00144h 00145h 00146h 00147h 00148h 00149h 0014ah 0014bh 0014ch 0014dh 0014eh 0014fh 00150h 00151h 00152h 00153h 00154h 00155h 00156h 00157h 00158h 00159h 0015ah 0015bh 0015ch 0015dh 0015eh 0015fh 00160h 00161h 00162h 00163h 00164h 00165h 00166h 00167h 00168h 00169h 0016ah 0016bh 0016ch 0016dh 0016eh 0016fh 00170h 00171h 00172h 00173h 00174h 00175h 00176h 00177h 00178h 00179h 0017ah 0017bh 0017ch 0017dh 0017eh 0017fh
r8c/m11a group, r8c/m12a group 3. address space r01ds0010ej0200 rev.2.00 page 21 of 45 may 31, 2012 note: 1. the blank areas are reserved. no access is allowed. table 3.7 sfr information (7) (1) address register name symbol after reset 00180h comparator b control register wcmpr 00h 00181h comparator b1 interrupt control register wcb1intr 00h 00182h comparator b3 interrupt control register wcb3intr 00h 00183h 00184h 00185h 00186h 00187h 00188h 00189h 0018ah 0018bh 0018ch 0018dh 0018eh 0018fh 00190h 00191h 00192h 00193h 00194h 00195h 00196h 00197h 00198h 00199h 0019ah 0019bh 0019ch 0019dh 0019eh 0019fh 001a0h 001a1h 001a2h 001a3h 001a4h 001a5h 001a6h 001a7h 001a8h 001a9h flash memory status register fst 10000000b 001aah flash memory control register 0 fmr0 00h 001abh flash memory control register 1 fmr1 00h 001ach flash memory control register 2 fmr2 00h 001adh flash memory refresh control register frefr 00h 001aeh 001afh 001b0h 001b1h 001b2h 001b3h 001b4h 001b5h 001b6h 001b7h 001b8h 001b9h 001bah 001bbh 001bch 001bdh 001beh 001bfh
r8c/m11a group, r8c/m12a group 3. address space r01ds0010ej0200 rev.2.00 page 22 of 45 may 31, 2012 note: 1. the blank areas are reserved. no access is allowed. table 3.8 sfr information (8) (1) address register name symbol after reset 001c0h address match interrupt register 0 aiadr0l 00h 001c1h aiadr0m 00h 001c2h aiadr0h 00h 001c3h address match interrupt enable register 0 aien0 00h 001c4h address match interrupt register 1 aiadr1l 00h 001c5h aiadr1m 00h 001c6h aiadr1h 00h 001c7h address match interrupt enable register 1 aien1 00h 001c8h 001c9h 001cah 001cbh 001cch 001cdh 001ceh 001cfh 001d0h 001d1h 001d2h 001d3h 001d4h 001d5h 001d6h 001d7h 001d8h 001d9h 001dah 001dbh 001dch 001ddh 001deh 001dfh 001e0h 001e1h 001e2h 001e3h 001e4h 001e5h 001e6h 001e7h 001e8h 001e9h 001eah 001ebh 001ech 001edh 001eeh 001efh 001f0h 001f1h 001f2h 001f3h 001f4h 001f5h 001f6h 001f7h 001f8h 001f9h 001fah 001fbh 001fch 001fdh 001feh 001ffh
r8c/m11a group, r8c/m12a group 3. address space r01ds0010ej0200 rev.2.00 page 23 of 45 may 31, 2012 notes: 1. the option function select area is allocated in the flash memory , not in the sfrs. set appropriate values as rom data by a pr ogram. do not perform an additional write to the option function select area. erasure of the block including the option function selec t area causes the option function select area to be set to ffh. when blank products are shipped, the option function select area is set to ffh. it is set to the written value after written by the user. when factory-programming products are shipped, the value of the option function select area is the value programmed by the user . 2. the id code area is allocated in the flash memory, not in the sfrs. set appropriate values as rom data by a program. do not perform an additional write to the id code area. erasure of the block including the id code area causes the id code area to be set to ffh. when blank products are shipped, the id code areas are set to ffh. they are set to the written value after written by the user. when factory-programming products are shipped, the value of the id code areas is the value programmed by the user. table 3.9 id code area and option function select area address area name symbol after reset : 0ffdbh option function select register 2 ofs2 (note 1) : 0ffdfh id1 (note 2) : 0ffe3h id2 (note 2) : 0ffebh id3 (note 2) : 0ffefh id4 (note 2) : 0fff3h id5 (note 2) : 0fff7h id6 (note 2) : 0fffbh id7 (note 2) : 0ffffh option function select register ofs (note 1)
r8c/m11a group, r8c/m12a group 4. electrical characteristics r01ds0010ej0200 rev.2.00 page 24 of 45 may 31, 2012 4. electrical characteristics note: 1. when the oscillation circuit is used: bits ckpt1 to ckpt0 in the exckcr register are set to 11b when the oscillation circuit is not used: bits ckpt1 to ckpt0 in the exckcr register are set to any value other than 11b table 4.1 absolute maximum ratings symbol parameter condition rated value unit v cc /av cc power supply voltage -0.3 to 6.5 v v i input voltage xin xin-xout oscillation on (oscillation circuit used) (1) -0.3 to 1.9 v xin-xout oscillation off (oscillation circuit not used) (1) -0.3 to vcc + 0.3 v other pins -0.3 to vcc + 0.3 v v o output voltage xout xin- xout oscillation on (oscillation circuit used) (1) -0.3 to 1.9 v xin-xout oscillation off (oscillation circuit not used) (1) -0.3 to vcc + 0.3 v other pins -0.3 to vcc + 0.3 v p d power consumption -40 c topr 85 c500mw t opr operating ambient temperature -20 to 85 (n version)/ -40 to 85 (d version) c t stg storage temperature -60 to 150 c
r8c/m11a group, r8c/m12a group 4. electrical characteristics r01ds0010ej0200 rev.2.00 page 25 of 45 may 31, 2012 notes: 1. vcc = 1.8 v to 5.5 v and topr = -20 c to 85 c (n version)/-40 c to 85 c (d version), unless otherwise specified. 2. the average output current indicates the average value of current measured during 100 ms. 3. for details, see table 4.10 high-speed on-chip oscillator circuit electrical characteristics . 4. for details, see table 4.11 low-speed on-chip oscillator circuit electrical characteristics . 5. the pins with high drive capa city are p1_2, p1_3, p1_4, p1_5, p3_3, p3_4, p3_5, and p3_7. figure 4.1 ports p1, p3, and p4 timing measurement circuit table 4.2 recommended operating conditions symbol parameter condition standard unit min. typ. max. v cc /av cc power supply voltage 1.8 ? 5.5 v v ss /av ss power supply voltage ? 0 ? v v ih input high voltage other than cmos input 0.8 vcc ? vcc v cmos input 4.0 v vcc 5.5 v 0.65 vcc ? vcc v 2.7 v vcc < 4.0 v 0.7 vcc ? vcc v 1.8 v vcc < 2.7 v 0.8 vcc ? vcc v v il input low voltage other than cmos input 0 ? 0.2 vcc v cmos input 4.0 v vcc 5.5 v 0 ? 0.4 vcc v 2.7 v vcc < 4.0 v 0 ? 0.3 vcc v 1.8 v vcc < 2.7 v 0 ? 0.2 vcc v i oh(sum) peak sum output high current sum of all pins i oh(peak) ? ? -160 ma i oh(sum) average sum output high current sum of all pins i oh(avg) ??-80ma i oh(peak) peak output high current when drive capacity is low ? ? -10 ma when drive capacity is high (5) ??-40ma i oh(avg) average output high current when drive capacity is low ? ? -5 ma when drive capacity is high (5) ??-20ma i ol(sum) peak sum output low current sum of all pins i ol(peak) ? ? 160 ma i ol(sum) average sum output low current sum of all pins i ol(avg) ??80ma i ol(peak) peak output low current when drive capacity is low ? ? 10 ma when drive capacity is high (5) ??40ma i ol(avg) average output low current when drive capacity is low ? ? 5 ma when drive capacity is high (5) ??20ma f (xin) xin oscillation frequency 2.7 v vcc 5.5 v 2 ? 20 mhz 1.8 v vcc < 2.7 v 2 ? 5 mhz xin clock input oscillation frequency 2.7 v vcc 5.5 v 0 ? 20 mhz 1.8 v vcc < 2.7 v 0 ? 5 mhz fhoco high-speed on-chip oscillat or oscillation frequency (3) 1.8 v vcc 5.5 v ? 20 ? mhz floco low-speed on-chip oscillat or oscillation frequency (4) 1.8 v vcc 5.5 v ? 125 ? khz ? system clock frequency 2.7 v vcc 5.5 v ? ? 20 mhz 1.8 v vcc < 2.7 v ? ? 5 mhz f s cpu clock frequency 2.7 v vcc 5.5 v 0 ? 20 mhz 1.8 v vcc < 2.7 v 0 ? 5 mhz p1 p3 p4 30 pf
r8c/m11a group, r8c/m12a group 4. electrical characteristics r01ds0010ej0200 rev.2.00 page 26 of 45 may 31, 2012 notes: 1. vcc/avcc = 1.8 v to 5.5 v and vss = 0 v and topr = -20 c to 85 c (n version)/-40 c to 85 c (d version), unless otherwise specified. 2. the a/d conversion result will be undefi ned in stop mode, or when the flash memory is in low-current-consumption read mode or stopped. do not perform a/d conversion in these stat es. do not enter these states during a/d conversion. notes: 1. vcc = 2.7 v to 5.5 v and topr = -20 c to 85 c (n version)/-40 c to 85 c (d version), unless otherwise specified. 2. when the digital filter is disabled. table 4.3 a/d converter characteristics symbol parameter condition standard unit min. typ. max. ? resolution ? ? 10 bit ? absolute accuracy avcc = 5.0 v an0 to an4, an7 input ? ? 3 lsb avcc = 3.0 v an0 to an4, an7 input ? ? 5 lsb avcc = 1.8 v an0 to an4, an7 input ? ? 5 lsb ? a/d conversion clock 4.0 v avcc 5.5 v (2) 2?20mhz 3.2 v avcc 5.5 v (2) 2?16mhz 2.7 v avcc 5.5 v (2) 2?10mhz 1.8 v avcc 5.5 v (2) 2?5mhz ? permissible signal source impedance 3k ? t conv conversion time avcc = 5.0 v, a/d conversion clock = 20 mhz 2.20 ? ? s t samp sampling time a/d conversion clock = 20 mhz 0.80 ? ? s v ia analog input voltage 0 ? avcc v table 4.4 comparator b electrical characteristics symbol parameter condition standard unit min. typ. max. v ref ivref1, ivref3 input reference voltage 0 ? vcc - 1.4 v v i ivcmp1, ivcmp3 input voltage -0.3 ? vcc + 0.3 v ?offset ? 5 100 mv t d comparator output delay time (2) v i = vref 100 mv ? 0.1 ? s i cmp comparator operating current vcc = 5.0 v ? 17.5 ? a
r8c/m11a group, r8c/m12a group 4. electrical characteristics r01ds0010ej0200 rev.2.00 page 27 of 45 may 31, 2012 notes: 1. vcc = 2.7 v to 5.5 v and topr = 0 c to 60 c, unless otherwise specified. 2. definition of program/erase endurance the number of program/erase cycles is defined on a per-block basis. if the number of cycles is 10,000, each block can be erased 10,000 times. for example, if 1,024 cycles of 1-byte-write are performed to different addresses in 1 kbyte of block a, and then the block is erased, the number of cycles is counted as one. note, however, that the same address must not be programmed more than once before completion of an erase (overwriting prohibited). 3. this indicates the number of times up to which all electr ical characteristics can be guaranteed after the last programming/ erase operation. operation is guaranteed for any number of oper ations in the range of 1 to the specified minimum (min). 4. in a system that executes multiple programming operations , the actual erase count can be reduced by shifting the write addresses in sequence and programming so that as much of the fl ash memory as possible is us ed before performing an erase operation. for example, when programming in 16-byte units, the effective number of rewrites can be minimized by programming up to 128 units before erasing them all in one oper ation. it is also advisable to retain data on the number of erase operations for each block and establish a limi t for the number of erase operations performed. 5. if an error occurs during a bl ock erase, execute a clear st atus register command and then a block erase command at least three times until the erase error does not occur. 6. for information on the program/erase failure rate, contact a renesas technical support representative. 7. the data hold time includes the time that the power supply is off and the time the clock is not supplied. table 4.5 flash memory (program rom) electrical characteristics symbol parameter condition standard unit min. typ. max. ? program/erase endurance (2) 10,000 (3) ??times ? byte programming time (program/erase endurance 1,000 times) ?80 ? s ? byte programming time (program/erase endurance > 1,000 times) ? 160 ? s ? block erase time ? 0.12 ? s t d(sr-sus) transition time to suspend ? ? 0.25 + cpu clock 3 cycles ms ? time from suspend until erase restart ? ? 30 + cpu clock 1 cycle s t d(cmdrst ready) time from when command is forcibly terminated until reading is enabled ? ? 30 + cpu clock 1 cycle s ? program/erase voltage 1.8 ? 5.5 v ? read voltage 1.8 ? 5.5 v ? program/erase temperature 0 ? 60 c ? data hold time (7) ambient temperature = 85 c 10 ? ? years
r8c/m11a group, r8c/m12a group 4. electrical characteristics r01ds0010ej0200 rev.2.00 page 28 of 45 may 31, 2012 notes: 1. vcc = 2.7 v to 5.5 v and topr = -20 c to 85 c (n version)/-40 c to 85 c (d version), unless otherwise specified. 2. definition of program/erase endurance the number of program/erase cycles is defined on a per-block basis. if the number of cycles is 10,000, each block can be erased 10,000 times. for example, if 1,024 cycles of 1-byte-write are performed to different addresses in 1 kbyte of block a, and then the block is erased, the number of cycles is counted as one. note, however, that the same address must not be programmed more than once before completion of an erase (overwriting prohibited). 3. this indicates the number of times up to which all electr ical characteristics can be guaranteed after the last programming/ erase operation. operation is guaranteed for any number of oper ations in the range of 1 to the specified minimum (min). 4. in a system that executes multiple program operations, the ac tual erase count can be reduced by shifting the write addresses in sequence and programming so that as mu ch of the flash memory as possible is used before performing an erase operation. for example, when programming in 16-byte units, the effective number of rewrites can be minimized by programming up to 128 units before erasing them all in one operation. it is also ad visable to retain data on the number of erase operations for each block and establish a limit for the number of erase operations performed. 5. if an error occurs during a bl ock erase, execute a clear st atus register command and then a block erase command at least three times until the erase error does not occur. 6. for information on the program/erase failure rate, contact a renesas technical support representative. 7. the data hold time includes the time that the power supply is off and the time the clock is not supplied. figure 4.2 transition time until suspend table 4.6 flash memory (blocks a and b of data flash) electrical characteristics symbol parameter condition standard unit min. typ. max. ? program/erase endurance (2) 10,000 (3) ??times ? byte programming time ? 150 ? s ? block erase time ? 0.05 1 s t d(sr-sus) time delay from suspend request until suspend ? ? 0.25 + cpu clock 3 cycles ms ? time from suspend until erase restart ? ? 30 + cpu clock 1 cycle s t d(cmdrst- ready) time from when command is forcibly stopped until reading is enabled ? ? 30 + cpu clock 1 cycle s ? program/erase voltage 1.8 ? 5.5 v ? read voltage 1.8 ? 5.5 v ? program/erase temperature -20 (n version) ?85 c -40 (d version) ?85 c ? data hold time (7) ambient temperature = 85 c 10 ? ? years suspend request (fmr21) fst6, fst7: bits in fst register fmr21: bit in fmr2 register fixed time fst6 clock-dependent time t d(sr-sus) access restart fst7
r8c/m11a group, r8c/m12a group 4. electrical characteristics r01ds0010ej0200 rev.2.00 page 29 of 45 may 31, 2012 notes: 1. the measurement condition is vcc = 1.8 v to 5.5 v and topr = -20 c to 85 c (n version)/-40 c to 85 c (d version). 2. select the voltage detection level with bits vdsel0 and vdsel1 in the ofs register. 3. the response time is from when the voltage passes vdet0 until the voltage monitor 0 reset is generated. 4. the wait time is necessary for the voltage detection circuit to operate when the vc0e bit in the vca2 register is set to 0 an d then 1. notes: 1. the measurement condition is vcc = 1.8 v to 5.5 v and topr = -20 c to 85 c (n version)/-40 c to 85 c (d version). 2. select the voltage detection level with bits vd1s1 to vd1s3 in the vd1ls register. 3. the response time is from when the voltage passes vdet1 until the voltage monitor 1 interrupt request is generated. 4. the wait time is necessary for the voltage detection circuit to operate when the vc1e bit in the vca2 register is set to 0 an d then 1. table 4.7 voltage detection 0 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det0 voltage detection level vdet0_0 (2) 1.80 1.90 2.05 v voltage detection level vdet0_1 (2) 2.15 2.35 2.50 v voltage detection level vdet0_2 (2) 2.70 2.85 3.05 v voltage detection level vdet0_3 (2) 3.55 3.80 4.05 v ? voltage detection 0 circuit response time (3) when vcc decreases from 5 v to (vdet0_0 - 0.1) v ?30? s ? self power consumption in voltage detection circuit vc0e = 1, vcc = 5.0 v ? 1.5 ? a t d(e-a) wait time until voltage detection circuit operation starts (4) ? ? 100 s table 4.8 voltage detection 1 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det1 voltage detection level vdet1_1 (2) when vcc decreases 2.15 2.35 2.55 v voltage detection level vdet1_3 (2) when vcc decreases 2.45 2.65 2.85 v voltage detection level vdet1_5 (2) when vcc decreases 2.75 2.95 3.15 v voltage detection level vdet1_7 (2) when vcc decreases 3.00 3.25 3.55 v voltage detection level vdet1_9 (2) when vcc decreases 3.30 3.55 3.85 v voltage detection level vdet1_b (2) when vcc decreases 3.60 3.85 4.15 v voltage detection level vdet1_d (2) when vcc decreases 3.90 4.15 4.45 v voltage detection level vdet1_f (2) when vcc decreases 4.20 4.45 4.75 v ? hysteresis width at the rising of vcc in voltage detection 1 circuit vdet1_1 to vdet1_5 selected ? 0.07 ? v vdet1_7 to vdet1_f selected ? 0.10 ? v ? voltage detection 1 circuit response time (3) when vcc decreases from 5 v to (vdet1_0 - 0.1) v ? 60 150 s ? self power consumption in voltage detection circuit vc1e = 1, vcc = 5.0 v ? 1.7 ? a t d(e-a) wait time until voltage detection circuit operation starts (4) ? ? 100 s
r8c/m11a group, r8c/m12a group 4. electrical characteristics r01ds0010ej0200 rev.2.00 page 30 of 45 may 31, 2012 notes: 1. the measurement condition is topr = -20 c to 85 c (n version)/-40 c to 85 c (d version), unless otherwise specified. 2. to use the power-on reset function, enable the voltage monito r 0 reset by setting the lvdas bit in the ofs register to 0. figure 4.3 power-on reset circui t electrical characteristics table 4.9 power-on reset circuit (2) symbol parameter condition standard unit min. typ. max. t rth external power vcc rise gradient 0 ? 50,000 mv/msec notes: 1. vdet0 indicates the voltage detection level of the voltage detection 0 circuit. for details, see 7. voltage detection circuit in the user?s manual: hardware. 2. t w(por) is required for a power-on reset to be enabled with the ex ternal power vcc held below the valid voltage (0.5 v) to enable a power-on reset. when vcc decreases with voltage m onitor 0 reset disabled and then turns on, maintain t w(por) for 1 ms or more. vdet0 (1) internal reset signal (low active) 0.5 v t w(por) (2) t rth voltage detection 0 circuit response time external power vcc t rth 256 1 floco 256 1 floco
r8c/m11a group, r8c/m12a group 4. electrical characteristics r01ds0010ej0200 rev.2.00 page 31 of 45 may 31, 2012 notes: 1. vcc = 1.8 v to 5.5 v, topr = -20 c to 85 c (n version)/-40 c to 85 c (d version), unless otherwise specified. 2. this enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0 % when the serial interface is used in uart mode. note: 1. vcc = 1.8 v to 5.5 v, topr = -20 c to 85 c (n version)/-40 c to 85 c (d version), unless otherwise specified. notes: 1. the measurement condition is vcc = 1.8 v to 5.5 v and topr = 25 c. 2. wait time until the internal power suppl y generation circuit stabilizes during power-on. table 4.10 high-speed on-chip oscillator circuit electrical characteristics symbol parameter package condition standard unit min. typ. max. ? high-speed on-chip oscillator frequency after reset is cleared 14-pin tssop 20-pin lssop vcc = 1.8 v to 5.5 v, -20 c to p r 85 c 19.2 20.0 20.8 mhz 14-pin dip 20-pin dip 19.0 20.0 21.0 mhz 14-pin tssop 20-pin lssop vcc = 1.8 v to 5.5 v, -40 c to p r 85 c 19.0 20.0 21.0 mhz high-speed on-chip oscillator frequency when the fr18s0 register adjustment value is written into the frv1 register and the fr18s1 register adjustment value into the frv2 register (2) 14-pin tssop 20-pin lssop vcc = 1.8 v to 5.5 v, -20 c to p r 85 c 17.694 18.432 19.169 mhz 14-pin dip 20-pin dip 17.510 18.432 19.353 mhz 14-pin tssop 20-pin lssop vcc = 1.8 v to 5.5 v, -40 c to p r 85 c 17.510 18.432 19.353 mhz ? oscillation stabilization time ? ? ? 30 s ? self power consumption at oscillation ? vcc = 5.0 v, topr = 25 c ? 530 ? a table 4.11 low-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. floco low-speed on-chip oscillator frequency 60 125 250 khz ? oscillation stabilization time ? ? 35 s ? self power consumption at oscillation vcc = 5.0 v, topr = 25 c?2? a table 4.12 power supply circuit timing characteristics symbol parameter condition standard unit min. typ. max. t d(p-r) time for internal power supply stabilization during power-on (2) ? ? 2,000 s
r8c/m11a group, r8c/m12a group 4. electrical characteristics r01ds0010ej0200 rev.2.00 page 32 of 45 may 31, 2012 notes: 1. 4.0 v vcc 5.5 v and topr = -20 c to 85 c (n version)/-40 c to 85 c (d version), f(xin) = 20 mhz, unless otherwise specified. 2. high drive capacity can also be used wh ile the peripheral output function is used. table 4.13 dc characteristics (1) [4.0 v vcc 5.5 v] symbol parameter condition standard unit min. typ. max. v oh output high voltage p1_2, p1_3, p1_4, p1_5, p3_3, p3_4, p3_5, p3_7 (2) when drive capacity is high i oh = -20 ma vcc - 2.0 ? vcc v when drive capacity is low i oh = -5 ma vcc - 2.0 ? vcc v p1_0, p1_1, p1_6, p1_7, p4_2, p4_5, p4_6, p4_7, pa_0 i oh = -5 ma vcc - 2.0 ? vcc v v ol output low voltage p1_2, p1_3, p1_4, p1_5, p3_3, p3_4, p3_5, p3_7 (2) when drive capacity is high i ol = 20 ma ? ? 2.0 v when drive capacity is low i ol = 5 ma ? ? 2.0 v p1_0, p1_1, p1_6, p1_7, p4_2, p4_5, p4_6, p4_7, pa_0 i ol = 5 ma ? ? 2.0 v v t +-v t - hysteresis int0 , int1 , int2 , int3 , ki0 , ki1 , ki2 , ki3 , trjio, trcioa, trciob, trcioc, trciod, rxd0, clk0 vcc = 5 v 0.1 1.2 ? v reset vcc = 5 v 0.1 1.2 ? v i ih input high current v i = 5 v, vcc = 5.0 v ? ? 5.0 a i il input low current v i = 0 v, vcc = 5.0 v ? ? -5.0 a r pullup pull-up resistance v i = 0 v, vcc = 5.0 v 25 50 100 k ? r fxin feedback resistance xin ? 2.2 ? m ? v ram ram hold voltage in stop mode 1.8 ? ? v
r8c/m11a group, r8c/m12a group 4. electrical characteristics r01ds0010ej0200 rev.2.00 page 33 of 45 may 31, 2012 notes: 1. vcc = 4.0 v to 5.5 v, single-chip mode, output pi ns are open, and other pins are connected to vss. 2. when the xin input is a square wave. 3. vcc = 5.0 v 4. set the system clock to 4 mhz with the phisel register. table 4.14 dc characteristics (2) [4.0 v vcc 5.5 v] (topr = -20 c to 85 c (n version)/-40 c to 85 c (d version), unless otherwise specified) symbol parameter condition unit oscillation circuit on-chip oscillator cpu clock low-power- consumption setting other standard xin (2) high- speed low- speed min. typ. (3) max. i cc power supply current (1) high-speed clock mode 20 mhz off 125 khz no division ??37.0ma 16 mhz off 125 khz no division ??2.56.0ma 10 mhz off 125 khz no division ??1.7?ma 20 mhz off 125 khz division by 8 ??1.5?ma 16 mhz off 125 khz division by 8 ??1.2?ma 10 mhz off 125 khz division by 8 ??1.0?ma high-speed on-chip oscillator mode off 20 mhz 125 khz no division ?3.57.5ma off 20 mhz 125 khz division by 8 ?2.0?ma off 4 mhz (4) 125 khz division by 16 msttrc = 1 ? 1.0 ? ma low-speed on-chip oscillator mode off off 125 khz division by 8 fmr27 = 1 lpe = 0 ?60270 a wait mode off off 125 khz ? vc1e = 0 vc0e = 0 lpe = 1 peripheral clock supplied during wait instruction execution ?15100 a off off 125 khz ? vc1e = 0 vc0e = 0 lpe = 1 wckstp = 1 peripheral clock stopped during wait instruction execution ?4.090 a stop mode off off off ? vc1e = 0 vc0e = 0 stpm = 1 topr = 25 c peripheral clock stopped ?1.04.0 a off off off ? vc1e = 0 vc0e = 0 stpm = 1 topr = 85 c peripheral clock stopped ?1.5? a
r8c/m11a group, r8c/m12a group 4. electrical characteristics r01ds0010ej0200 rev.2.00 page 34 of 45 may 31, 2012 timing requirements (vcc = 5 v, vss = 0 v at topr = 25 c, unless otherwise specified) figure 4.4 external clock input timing when vcc = 5 v figure 4.5 trjio input timing when vcc = 5 v table 4.15 external clock input (xin) symbol parameter standard unit min. max. t c(xin) xin input cycle time 50 ? ns t wh(xin) xin input high width 24 ? ns t wl(xin) xin input low width 24 ? ns table 4.16 trjio input symbol parameter standard unit min. max. t c(trjio) trjio input cycle time 100 ? ns t wh(trjio) trjio input high width 40 ? ns t wl(trjio) trjio input low width 40 ? ns vcc = 5 v external clock input t wh(xin) t c(xin) t wl(xin) vcc = 5 v trjio input t wh(trjio) t c(trjio) t wl(trjio)
r8c/m11a group, r8c/m12a group 4. electrical characteristics r01ds0010ej0200 rev.2.00 page 35 of 45 may 31, 2012 figure 4.6 serial interface timing when vcc = 5 v notes: 1. when the digital filter is enabled by the inti input filter select bit, the inti input high width is (1/digit al filter clock frequency 3) or the minimum value of the standard, whichever is greater. 2. when the digital filter is enabled by the inti input filter select bit, the inti input low width is (1/digital filter clock frequency 3) or the minimum value of the standard, whichever is greater. figure 4.7 timing for ex ternal interrupt inti input and key input interrupt kii when vcc = 5 v table 4.17 serial interface symbol parameter standard unit min. max. t c(ck) clk0 input cycle time 200 ? ns t w(ckh) clk0 input high width 100 ? ns t w(ckl) clk0 input low width 100 ? ns t d(c-q) txd0 output delay time ? 50 ns t h(c-q) txd0 hold time 0?ns t su(d-c) rxd0 input setup time 50 ? ns t h(c-d) rxd0 input hold time 90 ? ns table 4.18 external interrupt inti input, key input interrupt kii (i = 0 to 3) symbol parameter standard unit min. max. t w(inh) inti input high width, kii input high width 250 (1) ?ns t w(inl) inti input low width, kii input low width 250 (2) ?ns vcc = 5 v clk0 t w(ckh) t c(ck) t w(ckl) txd0 rxd0 t su(d-c) t d(c-q) t h(c-d) t h(c-q) vcc = 5 v inti input kii input (i = 0 to 3) t w(inl) t w(inh)
r8c/m11a group, r8c/m12a group 4. electrical characteristics r01ds0010ej0200 rev.2.00 page 36 of 45 may 31, 2012 notes: 1. 2.7 v vcc < 4.0 v and topr = -20 c to 85 c (n version)/-40 c to 85 c (d version), f(xin) = 10 mhz, unless otherwise specified. 2. high drive capacity can also be used wh ile the peripheral output function is used. table 4.19 dc characteristics (3) [2.7 v vcc < 4.0 v] symbol parameter condition standard unit min. typ. max. v oh output high voltage p1_2, p1_3, p1_4, p1_5, p3_3, p3_4, p3_5, p3_7 (2) when drive capacity is high i oh = -5 ma vcc - 0.5 ? vcc v when drive capacity is low i oh = -1 ma vcc - 0.5 ? vcc v p1_0, p1_1, p1_6, p1_7, p4_2, p4_5, p4_6, p4_7, pa_0 i oh = -1 ma vcc - 0.5 ? vcc v v ol output low voltage p1_2, p1_3, p1_4, p1_5, p3_3, p3_4, p3_5, p3_7 (2) when drive capacity is high i ol = 5 ma ? ? 0.5 v when drive capacity is low i ol = 1 ma ? ? 0.5 v p1_0, p1_1, p1_6, p1_7, p4_2, p4_5, p4_6, p4_7, pa_0 i ol = 1 ma ? ? 0.5 v v t +-v t -hysteresis int0 , int1 , int2 , int3 , ki0 , ki1 , ki2 , ki3 , trjio, trcioa, trciob, trcioc, trciod, rxd0, clk0 vcc = 3 v 0.1 0.4 ? v reset vcc = 3 v 0.1 0.5 ? v i ih input high current v i = 3 v, vcc = 3.0 v ? ? 4.0 a i il input low current v i = 0 v, vcc = 3.0 v ? ? -4.0 a r pullup pull-up resistance v i = 0 v, vcc = 3.0 v 42 84 168 k ? r fxin feedback resistance xin ? 2.2 ? m ? v ram ram hold voltage in stop mode 1.8 ? ? v
r8c/m11a group, r8c/m12a group 4. electrical characteristics r01ds0010ej0200 rev.2.00 page 37 of 45 may 31, 2012 notes: 1. vcc = 2.7 v to 4.0 v, single-chip mode, output pi ns are open, and other pins are connected to vss. 2. when the xin input is a square wave. 3. vcc = 3.0 v 4. set the system clock to 10 mhz or 4 mhz with the phisel register. table 4.20 dc characteristics (4) [2.7 v vcc < 4.0 v] (topr = -20 c to 85 c (n version)/-40 c to 85 c (d version), unless otherwise specified) symbol parameter condition unit oscillation circuit on-chip oscillator cpu clock low-power- consumption setting other standard xin (2) high- speed low- speed min. typ. (3) max. i cc power supply current (1) high-speed clock mode 20 mhz off 125 khz no division ??3.07.0ma 16 mhz off 125 khz no division ??2.56.0ma 10 mhz off 125 khz no division ??1.65.0ma 20 mhz off 125 khz division by 8 ??1.5?ma 16 mhz off 125 khz division by 8 ??1.2?ma 10 mhz off 125 khz division by 8 ??0.94.5ma high-speed on-chip oscillator mode off 20 mhz 125 khz no division ?3.57.5ma off 20 mhz 125 khz division by 8 ?2.0?ma off 10 mhz (4) 125 khz no division ?2.2?ma off 10 mhz (4) 125 khz division by 8 ?1.4?ma off 4 mhz (4) 125 khz division by 16 msttrc = 1 ? 1.0 ? ma low-speed on-chip oscillator mode off off 125 khz division by 8 fmr27 = 1 lpe = 0 ?60260 a wait mode off off 125 khz ? vc1e = 0 vc0e = 0 lpe = 1 peripheral clock supplied during wait instruction execution ?1590 a off off 125 khz ? vc1e = 0 vc0e = 0 lpe = 1 wckstp = 1 peripheral clock stopped during wait instruction execution ?4.080 a stop mode off off off ? vc1e = 0 vc0e = 0 stpm = 1 topr = 25 c peripheral clock stopped ?1.04.0 a off off off ? vc1e = 0 vc0e = 0 stpm = 1 topr = 85 c peripheral clock stopped ?1.5? a
r8c/m11a group, r8c/m12a group 4. electrical characteristics r01ds0010ej0200 rev.2.00 page 38 of 45 may 31, 2012 timing requirements (vcc = 3 v, vss = 0 v at topr = 25 c, unless otherwise specified) figure 4.8 external clock input timing when vcc = 3 v figure 4.9 trjio input timing when vcc = 3 v table 4.21 external clock input (xin) symbol parameter standard unit min. max. t c(xin) xin input cycle time 50 ? ns t wh(xin) xin input high width 24 ? ns t wl(xin) xin input low width 24 ? ns table 4.22 trjio input symbol parameter standard unit min. max. t c(trjio) trjio input cycle time 300 ? ns t wh(trjio) trjio input high width 120 ? ns t wl(trjio) trjio input low width 120 ? ns vcc = 3 v external clock input t wh(xin) t c(xin) t wl(xin) vcc = 3 v trjio input t wh(trjio) t c(trjio) t wl(trjio)
r8c/m11a group, r8c/m12a group 4. electrical characteristics r01ds0010ej0200 rev.2.00 page 39 of 45 may 31, 2012 figure 4.10 serial interface timing when vcc = 3 v notes: 1. when the digital filter is enabled by the inti input filter select bit, the inti input high width is (1/digit al filter clock frequency 3) or the minimum value of the standard, whichever is greater. 2. when the digital filter is enabled by the inti input filter select bit, the inti input low width is (1/digital filter clock frequency 3) or the minimum value of the standard, whichever is greater. figure 4.11 timing for external interrupt inti input and key input interrupt kii when vcc = 3 v table 4.23 serial interface symbol parameter standard unit min. max. t c(ck) clk0 input cycle time 300 ? ns t w(ckh) clk0 input high width 150 ? ns t w(ckl) clk0 input low width 150 ? ns t d(c-q) txd0 output delay time ? 80 ns t h(c-q) txd0 hold time 0?ns t su(d-c) rxd0 input setup time 70 ? ns t h(c-d) rxd0 input hold time 90 ? ns table 4.24 external interrupt inti input, key input interrupt kii (i = 0 to 3) symbol parameter standard unit min. max. t w(inh) inti input high width, kii input high width 380 (1) ?ns t w(inl) inti input low width, kii input low width 380 (2) ?ns vcc = 3 v clk0 t w(ckh) t c(ck) t w(ckl) txd0 rxd0 t su(d-c) t d(c-q) t h(c-d) t h(c-q) vcc = 3 v inti input kii input (i = 0 to 3) t w(inl) t w(inh)
r8c/m11a group, r8c/m12a group 4. electrical characteristics r01ds0010ej0200 rev.2.00 page 40 of 45 may 31, 2012 notes: 1. 1.8 v vcc < 2.7 v and topr = -20 c to 85 c (n version)/-40 c to 85 c (d version), f(xin) = 5 mhz, unless otherwise specified. 2. high drive capacity can also be used wh ile the peripheral output function is used. table 4.25 dc characteristics (5) [1.8 v vcc < 2.7 v] symbol parameter condition standard unit min. typ. max. v oh output high voltage p1_2, p1_3, p1_4, p1_5, p3_3, p3_4, p3_5, p3_7 (2) when drive capacity is high i oh = -2 ma vcc - 0.5 ? vcc v when drive capacity is low i oh = -1 ma vcc - 0.5 ? vcc v p1_0, p1_1, p1_6, p1_7, p4_2, p4_5, p4_6, p4_7, pa_0 i oh = -1 ma vcc - 0.5 ? vcc v v ol output low voltage p1_2, p1_3, p1_4, p1_5, p3_3, p3_4, p3_5, p3_7 (2) when drive capacity is high i ol = 2 ma ? ? 0.5 v when drive capacity is low i ol = 1 ma ? ? 0.5 v p1_0, p1_1, p1_6, p1_7, p4_2, p4_5, p4_6, p4_7, pa_0 i ol = 1 ma ? ? 0.5 v v t +-v t -hysteresis int0 , int1 , int2 , int3 , ki0 , ki1 , ki2 , ki3 , trjio, trcioa, trciob, trcioc, trciod, rxd0, clk0 vcc = 2.2 v 0.05 0.20 ? v reset vcc = 2.2 v 0.05 0.20 ? v i ih input high current v i = 2.2 v, vcc = 2.2 v ? ? 4.0 a i il input low current v i = 0 v, vcc = 2.2 v ? ? -4.0 a r pullup pull-up resistance v i = 0 v, vcc = 2.2 v 70 140 300 k ? r fxin feedback resistance xin ? 2.2 ? m ? v ram ram hold voltage in stop mode 1.8 ? ? v
r8c/m11a group, r8c/m12a group 4. electrical characteristics r01ds0010ej0200 rev.2.00 page 41 of 45 may 31, 2012 notes: 1. vcc = 1.8 v to 2.7 v, single-chip mode, output pi ns are open, and other pins are connected to vss. 2. when the xin input is a square wave. 3. vcc = 2.2 v 4. set the system clock to 5 mhz or 4 mhz with the phisel register. table 4.26 dc characteristics (6) [1.8 v vcc < 2.7 v] (topr = -20 c to 85 c (n version)/-40 c to 85 c (d version), unless otherwise specified) symbol parameter condition unit oscillation circuit on-chip oscillator cpu clock low-power- consumption setting other standard xin (2) high- speed low- speed min. typ. (3) max. i cc power supply current (1) high-speed clock mode 5 mhz off 125 khz no division ??1.0?ma 5 mhz off 125 khz division by 8 ??0.6?ma high-speed on-chip oscillator mode off 5 mhz (4) 125 khz no division ?1.66.5ma off 5 mhz (4) 125 khz division by 8 ?1.1?ma off 4 mhz (4) 125 khz division by 16 msttrc = 1 ? 1.0 ? ma low-speed on-chip oscillator mode off off 125 khz division by 8 fmr27 = 1 lpe = 0 ?60200 a wait mode off off 125 khz ? vc1e = 0 vc0e = 0 lpe = 1 peripheral clock supplied during wait instruction execution ?1590 a off off 125 khz ? vc1e = 0 vc0e = 0 lpe = 1 wckstp = 1 peripheral clock stopped during wait instruction execution ?4.080 a stop mode off off off ? vc1e = 0 vc0e = 0 stpm = 1 topr = 25 c peripheral clock stopped ?1.04.0 a off off off ? vc1e = 0 vc0e = 0 stpm = 1 topr = 85 c peripheral clock stopped ?1.5? a
r8c/m11a group, r8c/m12a group 4. electrical characteristics r01ds0010ej0200 rev.2.00 page 42 of 45 may 31, 2012 timing requirements (vcc = 2.2 v, vss = 0 v at topr = 25 c, unless otherwise specified) figure 4.12 external clock input timing when vcc = 2.2 v figure 4.13 trjio input ti ming when vcc = 2.2 v table 4.27 external clock input (xin) symbol parameter standard unit min. max. t c(xin) xin input cycle time 200 ? ns t wh(xin) xin input high width 90 ? ns t wl(xin) xin input low width 90 ? ns table 4.28 trjio input symbol parameter standard unit min. max. t c(trjio) trjio input cycle time 500 ? ns t wh(trjio) trjio input high width 200 ? ns t wl(trjio) trjio input low width 200 ? ns vcc = 2.2 v external clock input t wh(xin) t c(xin) t wl(xin) vcc = 2.2 v trjio input t wh(trjio) t c(trjio) t wl(trjio)
r8c/m11a group, r8c/m12a group 4. electrical characteristics r01ds0010ej0200 rev.2.00 page 43 of 45 may 31, 2012 figure 4.14 serial interface timing when vcc = 2.2 v notes: 1. when the digital filter is enabled by the inti input filter select bit, the inti input high width is (1/digit al filter clock frequency 3) or the minimum value of the standard, whichever is greater. 2. when the digital filter is enabled by the inti input filter select bit, the inti input low width is (1/digital filter clock frequency 3) or the minimum value of the standard, whichever is greater. figure 4.15 timing for external interrupt inti input and key input interrupt kii when vcc = 2.2 v table 4.29 serial interface symbol parameter standard unit min. max. t c(ck) clk0 input cycle time 800 ? ns t w(ckh) clk0 input high width 400 ? ns t w(ckl) clk0 input low width 400 ? ns t d(c-q) txd0 output delay time ? 200 ns t h(c-q) txd0 hold time 0?ns t su(d-c) rxd0 input setup time 150 ? ns t h(c-d) rxd0 input hold time 90 ? ns table 4.30 external interrupt inti input, key input interrupt kii (i = 0 to 3) symbol parameter standard unit min. max. t w(inh) inti input high width, kii input high width 1,000 (1) ?ns t w(inl) inti input low width, kii input low width 1,000 (2) ?ns vcc = 2.2 v clk0 t w(ckh) t c(ck) t w(ckl) txd0 rxd0 t su(d-c) t d(c-q) t h(c-d) t h(c-q) vcc = 2.2 v inti input kii input (i = 0 to 3) t w(inl) t w(inh)
r8c/m11a group, r8c/m12a group package dimensions r01ds0010ej0200 rev.2.00 page 44 of 45 may 31, 2012 package dimensions diagrams showing the latest package dimensions and moun ting information are available in the ?p ackages? section of the renesas electronics website. note) 1. dimensions" * 1 (nom)"and" * 2" do not include mold flash. 2. dimension" * 3"does not include trim offset. terminal cross section (ni/pd/au plating) c detail f l index mark f * 1 * 2 * 3 b p h e m x 17 14 8 s s y e z e d a p-tssop14-4.4x5-0.65 0.05g mass[typ.] ttp-14dv ptsp0014ja-b renesas code jeita package code previous code 0.83 0.10 0.65 6.20 6.60 0.20 0.15 5.30 max nom min dimension in millimeters symbol reference 1.10 0.6 0.5 0.4 4.40 0.10 0.07 0.03 0.25 0.20 0.15 0.10 6.40 8 0 0.13 1.0 5.00 e h e l a d e a 2 a 1 b p b 1 c x y z l 1 c 1 l 1 b p a 1 include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2. e 1 e * 2 * 3 8 14 7 1 seating plane * 1 z d b p c a 1 e b 3 d a 2 a l 6.45 19.4 6.25 19.2 2.92 a 2 l e 1 c a 1 0.5 a 4.8 e 6.35 d 19.3 7.69 reference symbol dimension in millimeters min nom max b 3 b p 0.38 0.55 1.47 1.52 1.57 3.05 3.25 3.45 0.21 0.35 e 2.54 0 15 p-dip14-6.35x19.3-2.54 0.94g mass[typ.] 14p4x-a prdp0014ac-a renesas code jeita package code previous code z d 2.03
r8c/m11a group, r8c/m12a group package dimensions r01ds0010ej0200 rev.2.00 page 45 of 45 may 31, 2012 index mark 1 10 11 20 f * 1 * 3 * 2 c b p e a d e h e include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2. detail f a 1 a 2 l 0.32 0.22 0.17 b p previous code jeita package code renesas code plsp0020jb-a 20p2f-a mass[typ.] 0.1g p-lssop20-4.4x6.5-0.65 0.2 0.15 0.13 max nom min dimension in millimeters symbol reference 6.6 6.5 6.4 d 4.5 4.4 4.3 e 1.15 a 2 6.6 6.4 6.2 1.45 a 0.2 0.1 0 0.7 0.5 0.3 l 10 0 c 0.65 e 0.10 y h e a 1 0.53 0.77 y s s include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2. 7.1 26.9 6.1 24.9 2.9 0 15 a 2 l e 1 c a 1 0.38 a 5.33 e 6.6 d 25.9 7.69 reference symbol dimension in millimeters min nom max b 3 b p 0.36 0.46 0.56 1.32 1.52 1.72 3.1 3.3 3.5 0.21 0.35 e 2.54 p-dip20-6.6x25.9-2.54 1.39g mass[typ.] 20p4x-a prdp0020ad-a renesas code jeita package code previous code z d 1.52 e e 1 * 2 * 3 11 20 10 1 seating plane * 1 la z d a 1 b p c e b 3 d a 2
c - 1 r8c/m11a group, r8c/m12a group datasheet rev. date description page summary 0.01 jan 14, 2010 ? first edition issued 0.10 aug 25, 2010 ? docume nt no. ?rej03b0308? ?r01ds0010ej? 2, 3 1.1.2 differences between groups added 4 table 1.3 ?reset by vo ltage detection 0? deleted 5 table 1.4 ?... rom: v cc = 2.7 v to 5.5 v? ?... rom: vcc = 1.8 v to 5.5 v?, ?1,000 times (program rom)? ?10,000 times (program rom)?, note 1 added 6 table 1.5 revised 8 figures 1.3 and 1.4 revised 9 table 1.6 revised 11 to 43 2. central processing unit (cpu), 3. address space, 4. electrical characteristics added 1.00 may 31, 2012 all pages ?preliminary? and ?under development? deleted 1 1.1 revised 3 table 1.2 revised 4 table 1.3 revised 5 table 1.4 note 1 revised 6 table 1.5 revised 10 table 1.7 revised 15 table 3.1 revised 18 table 3.4 revised 23 table 3.9 notes 1 and 2 revised 26 table 4.3 revised 31 table 4.10 and 4.11 revised, note3 deleted 45 package added 2.00 may 31, 2012 4 ?under development? deleted 9 table 1.6 ?voltage detection circuit? deleted 26 table 4.3 revised all trademarks and registered trademarks are the property of their respective owners. revision history
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? ? reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? ? ?
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